There are a variety of analog-to-digital ("A/D") converters. For example, there are parallel encoder (or flash) A/D converters, multistage A/D converters, successive approximation A/D converters, voltage-to-frequency A/D converters, dual-ramp A/D converters, and staircase A/D converters. There is such a variety because the need for converters has heightened with the advent of single-chip large scale integration ("LSI") microprocessors. In fact, in some cases, it is desirable to include such converters on the same chip with the microprocessor.
In many cases, there is the desire to have very fast conversion to maintain the speed of the overall system. The types of A/D converters typically used in these situations have been flash and multistage flash A/D converters. As larger and larger A/D converters were being constructed, the resulting large dies had a great deal of parasitics that had to be driven. This forced the technology in the opposite direction, which was to make the A/D converters smaller and smaller. This brought about the advent of the consideration of replacing flash and multistage flash A/D converters with serial-type A/D converters because in many ways they were easier to construct on a chip than multistage flash A/D converters and they can, in some cases, achieve the speed of flash A/D converters with considerably less power.
Serial-type A/D converters typically convert analog signals first into Gray scale code and then into binary code. They are configured to have a series of cascaded analog cells to which the Gray scale code-to-binary processing system connects. Each cell of the series of cascaded analog cells has a folding cell that will process the differential input signals, V.sub.IL and V.sub.IH, according to FIG. 1.
The signals input to the differential input of the folding cell are shown in FIG. 1A. As V.sub.IH increases and V.sub.IL decreases, there is a single crossing at 100. This is the place where the comparator of the folding cell is tripped and the V.sub.IH and V.sub.IL signals are folded to form the intermediate signals V.sub.1 and V.sub.2 that are shown in FIG. 1B. These intermediate signals are output from the current switching portion of the folding cell. When V.sub.1 and V.sub.2 are folded as shown in FIG. 1B, the folded signals converge but do not cross as shown at 102.
In order to obtain the desired V.sub.OH and V.sub.OL outputs for input to the next stage, it is necessary to further process the V.sub.1 and V.sub.2 signals. The processing that is necessary is to offset the V.sub.1 and V.sub.2 signals to align them. Once the offset has been applied, the alignment shown in FIG. 1C results. This alignment has crossing points at 104 and at 106. Thereafter, the V.sub.OH and V.sub.OL signals are input to the next stage of the serial-type A/D converter.
The folding cells of serial-type A/D converter have taken many configurations, one of which is a magnitude amplifier ("magamp") with offset circuitry that is either incorporated directly as part of the magamp or as separate circuitry that connects to the magamp. A concern of magamps, as with other types of folding cells, is the amount of parasitics that have to be driven. The greater the amount of parasitic capacitance loading that is realized, the slower the magamp, and, therefore, the A/D converter. This is of great concern because of the desire for the A/D conversion process to keep up with the remainder of the system and not constitute a bottleneck.
The present invention significantly reduces the parasitics in magamps at the load resistors. The present invention will be described in detail in the remainder of the specification referring to the drawings.